(a) Field of the Invention
The present invention relates to a circuit board preferably used in a semiconductor device such as having a land grid array (LGA) and a ball grid array (BGA).
(b) Description of the Related Art
Recently, a multi-layered circuit board of higher integration is required for fabricating a semiconductor device package with smaller dimensions.
The circuit board for meeting the above requirement generally includes a base member mounting thereon a plurality of interconnect layers which sandwich dielectric layers therebetween. The base member includes a first and a second interconnect layers on the respective surfaces thereof, and the interconnect layers are connected with each other through a via-hole formed in the base member.
In such a circuit board, a relatively large part of the dielectric layer is externally exposed. When the circuit board is exposed to a higher humidity atmosphere, moisture enters into the rear surface of the dielectric layer through the externally exposed portion.
When the first and the second interconnect layers are formed by conductive materials having different coefficients of thermal expansion, a crack may be generated in the circuit board by the warp in case of a rapid temperature change.
The above problem incurs lower reliability of such as having a lower packaging rank and failing in the temperature cycle test. In order to suppress the above problem, it is proposed that the interconnect layers and the dielectric layers be formed by materials having substantially same coefficients of thermal expansion or the thicknesses of the respective interconnect layers be increased.
However, the selection of the specific materials at the time of fabricating the circuit boars is burdensome and raises the cost. Further, the increased thickness makes the entire circuit board larger not to meet the recent demand of the miniaturization.
JP-A-6(1994)-69212 describes a circuit board including a dummy conductive film covering an interconnect conductive film with an intervention of a dielectric film. JP-A-7(1995)-154039 describes a circuit board including a dummy conductive pattern formed in a dielectric region having a specific area larger than a circle having a radius of 1 mm. JP-A-10(1998)-341077 describe a circuit board including a dummy conductive layer covering an opening of a via-hole with an intervention of a dielectric film. Although each of the above publications describes suppression (prevention) of the crack generation, none of them describes a method for overcoming the ingress of the moisture into the rear surface of the dielectric layer.
JP-A-11(1999)-154679 describes a circuit board including a dummy via-hole in the vicinity of a via-hole. JP-A-11(1999)-260962 describes a circuit board including a dummy interconnect projected from a conductive interconnect. Although each of these publications describes the prevention of the film peeling-off at the bottom surface of the via hole by dispersing a stress, and the suppression of the increase of the thermal distortion by elevating the rigidity of the dielectric film, none of them describes a method for overcoming the ingress of the moisture into the rear surface of the dielectric layer, similarly to the above publications.